When you EX a BAL instruction, where is the return address?

Mainframers
1

I have looked, and the answer to this question is certainly not obvious.
And I’d like to use it in some code I’m writing.

When you EXecute a BAL instruction, where is the return address set?
Following the EX instruction, or the BAL instruction?

To test, I wrote this code. Control came back following the EX instruction.
My question would be, “Is this how it works on a mainframe?”

------------- the comment processor certainly doesn’t like asterisks. And messes with formatting. And makes some stuff bold. That’s weird, but okay.
3times … LA … R3,3
EXBAL … EX … R0,BAL
BCT … BCT … R3,EXBAL
EXEX … EX … 0,EXEX

BAL … BAL … 4,BRR4
… DC … H’0’

BRR4 … BR … R4

… DC … H’0’

This ended with a X0C3, not S0C1. and R3 was 0…

my testing, on the z390 simulator, indicates that after EX-BAL,
control comes back following the EX instruction, not the BAL inst.

I assume that’s how it’s supposed to work.
But I don’t have a mainframe to test with.
This is the trace, when the code abended.

EZ390I Trace Table Entry 800FF05A 4400D066 EX
EZ390I Trace Table Entry 800FF066 4540D06C BAL
EZ390I Trace Table Entry 800FF06C 07F4 BR
EZ390I Trace Table Entry 800FF05E 4630D05A BCT
EZ390I Trace Table Entry 800FF05A 4400D066 EX
EZ390I Trace Table Entry 800FF066 4540D06C BAL
EZ390I Trace Table Entry 800FF06C 07F4 BR
EZ390I Trace Table Entry 800FF05E 4630D05A BCT
EZ390I Trace Table Entry 800FF062 4400D062 EX
EZ390E error 11 ABEND PSW=07850600 800FF062 4400D062 EX ABEND S0C3

–

R0-R3 F4F4F4F4800FF000 F4F4F4F400002300 F4F4F4F4F4F4F4F4 F4F4F4F400000000
R4-R7 F4F4F4F4800FF05E F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4
R8-RB F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4
RC-RF F4F4F4F4F4F4F4F4 F4F4F4F4800FF000 F4F4F4F400002018 F4F4F4F4800FF000
EZ390E error 12 program aborting due to abend S0C3

2

Are you sure it is ok to use Register 0 in the EEX instruction? (it has been awhile, but using r0 seems suspect because EX ors operand1 with the length operand of the object instruction (or something like that, it has been awhile, believe what the POO manual says)

3

The PSW remains at the position of the EX instruction, so the BAL is evaluated as though it were executed at that position. Just as processing resumes after the EX regardless what instruction you process (assuming it’s not a branching instruction). The BAL places the Next Sequential Instruction address in the referenced register and that address is the NSI of the EX.

4

CP, thank you. I’d hoped that’s how it worked.

Jack, when you EX an EX instruction, you get a S0C3 abend.
It’s always intentional. And it preserves ALL the registers.
IBM uses it all the time. Because it’s never accidental.